Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Nov 7 17:47:33 2023 Info: Command: quartus_sh --flow compile ap_core Info: Quartus(args): compile ap_core Info: Project Name = /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/ap_core Info: Revision Name = ap_core Info (293031): Detected changes in Quartus Prime Settings File (.qsf). Info (293028): Assignment ROUTER_TIMING_OPTIMIZATION_LEVEL changed value from MAXIMUM to NORMAL. Info (293028): Assignment PLACEMENT_EFFORT_MULTIPLIER changed value from 4.0 to 1.0. Info (293031): Detected changes in Quartus Prime Settings File (.qsf). Info (293028): Assignment ROUTER_TIMING_OPTIMIZATION_LEVEL changed value from MAXIMUM to NORMAL. Info (293028): Assignment PLACEMENT_EFFORT_MULTIPLIER changed value from 4.0 to 1.0. Info (293031): Detected changes in Quartus Prime Settings File (.qsf). Info (293028): Assignment ROUTER_TIMING_OPTIMIZATION_LEVEL changed value from MAXIMUM to NORMAL. Info (293028): Assignment PLACEMENT_EFFORT_MULTIPLIER changed value from 4.0 to 1.0. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition Info: Processing started: Tue Nov 7 17:47:33 2023 Info: Command: quartus_sh -t apf/build_id_gen.tcl compile ap_core ap_core Info: Quartus(args): compile ap_core ap_core Info: APF core build date/time generated: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/build_id.mif Info (23030): Evaluation of Tcl script apf/build_id_gen.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 478 megabytes Info: Processing ended: Tue Nov 7 17:47:33 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 Info (293003): Smart recompilation skipped module Analysis & Synthesis because it is not required Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition Info: Processing started: Tue Nov 7 17:47:34 2023 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off ap_core -c ap_core Info: qfit2_default_script.tcl version: #1 Info: Project = ap_core Info: Revision = ap_core Warning (20013): Ignored 16 assignments for entity "mf_pllbase" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_pll -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_VERSION 18.1 -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20013): Ignored 317 assignments for entity "mf_pllbase_0002" -- entity does not exist in design Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit) Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected Info (119006): Selected device 5CEBA4F23C8 for design "ap_core" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (184020): Starting Fitter periphery placement operations Info (11191): Automatically promoted 2 clocks (2 global) Info (11162): clk_74a~inputCLKENA0 with 1338 fanout uses global clock CLKCTRL_G6 Info (11162): bridge_spiclk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G10 Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays Warning (16406): 1 global input pin(s) will use non-dedicated clock routing Warning (16407): Source REFCLK I/O is not placed onto a dedicated REFCLK input pin for global clock driver bridge_spiclk~inputCLKENA0, placed at CLKCTRL_G10 Info (179012): Refclk input I/O pad bridge_spiclk is placed onto PIN_T17 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Info (332104): Reading SDC File: 'apf/apf_constraints.sdc' Info (332104): Reading SDC File: 'core/core_constraints.sdc' Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Info (332050): set_clock_groups -asynchronous \ -group { bridge_spiclk } \ -group { clk_74a } \ -group { clk_74b } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(16): core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] could not be matched with a port File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(16): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0]] -phase 0 -name vid_0 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332174): Ignored filter at core_constraints.sdc(17): core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] could not be matched with a port File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(17): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15]] -phase 90 -name vid_90 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332104): Reading SDC File: 'core/core_constraints.sdc' Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Info (332050): set_clock_groups -asynchronous \ -group { bridge_spiclk } \ -group { clk_74a } \ -group { clk_74b } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(16): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0]] -phase 0 -name vid_0 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(17): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15]] -phase 90 -name vid_90 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFLO is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFHI0 is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 3 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 13.468 bridge_spiclk Info (332111): 13.468 clk_74a Info (332111): 13.468 clk_74b Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Info (128000): Starting physical synthesis optimizations for speed Info (128002): Starting physical synthesis algorithm register retiming Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 167 ps Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128002): Starting physical synthesis algorithm register retiming Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:03 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:07 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 1% of the available device resources Info (170196): Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X44_Y11 to location X54_Y22 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:03 Info (11888): Total time spent on timing analysis during the Fitter is 2.32 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:07 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169064): Following 117 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results Info (169065): Pin cart_tran_bank2[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank2[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 57 Info (169065): Pin cart_tran_bank3[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank3[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 61 Info (169065): Pin cart_tran_bank1[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank1[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 65 Info (169065): Pin cart_tran_bank0[4] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 73 Info (169065): Pin cart_tran_bank0[5] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 73 Info (169065): Pin cart_tran_bank0[6] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 73 Info (169065): Pin cart_tran_bank0[7] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 73 Info (169065): Pin cart_tran_pin30 has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 77 Info (169065): Pin cart_tran_pin31 has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 86 Info (169065): Pin port_tran_si has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 96 Info (169065): Pin port_tran_so has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 98 Info (169065): Pin port_tran_sck has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 100 Info (169065): Pin port_tran_sd has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 102 Info (169065): Pin scal_vid[0] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[1] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[2] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[3] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[4] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[5] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[6] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[7] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[8] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[9] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[10] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_vid[11] has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 108 Info (169065): Pin scal_clk has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 109 Info (169065): Pin scal_de has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 110 Info (169065): Pin scal_skip has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 111 Info (169065): Pin scal_vs has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 112 Info (169065): Pin scal_hs has a permanently enabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 113 Info (169065): Pin cram0_dq[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[8] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[9] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[10] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[11] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[12] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[13] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[14] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram0_dq[15] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 134 Info (169065): Pin cram1_dq[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[8] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[9] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[10] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[11] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[12] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[13] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[14] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin cram1_dq[15] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 147 Info (169065): Pin dram_dq[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[8] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[9] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[10] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[11] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[12] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[13] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[14] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin dram_dq[15] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 164 Info (169065): Pin sram_dq[0] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[1] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[2] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[3] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[4] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[5] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[6] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[7] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[8] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[9] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[10] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[11] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[12] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[13] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[14] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin sram_dq[15] has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 176 Info (169065): Pin bist has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 202 Info (169065): Pin aux_sda has a permanently disabled output enable File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/apf/apf_top.v Line: 208 Info (144001): Generated suppressed messages file /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/output_files/ap_core.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 32 warnings Info: Peak virtual memory: 2480 megabytes Info: Processing ended: Tue Nov 7 17:48:14 2023 Info: Elapsed time: 00:00:40 Info: Total CPU time (on all processors): 00:02:20 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition Info: Processing started: Tue Nov 7 17:48:15 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ap_core -c ap_core Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Warning (12914): The file, /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/db/stp1_auto_stripped.stp, is not embedded into sof file as expected. Some tools, such as System Console, may not function fully. Info: Quartus Prime Assembler was successful. 0 errors, 2 warnings Info: Peak virtual memory: 516 megabytes Info: Processing ended: Tue Nov 7 17:48:18 2023 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:03 Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition Info: Processing started: Tue Nov 7 17:48:19 2023 Info: Command: quartus_sta ap_core -c ap_core Info: qsta_default_script.tcl version: #1 Warning (20013): Ignored 16 assignments for entity "mf_pllbase" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_pll -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_VERSION 18.1 -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20014): Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mf_pllbase -sip core/mf_pllbase.sip -library lib_mf_pllbase was ignored Warning (20013): Ignored 317 assignments for entity "mf_pllbase_0002" -- entity does not exist in design Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332104): Reading SDC File: 'apf/apf_constraints.sdc' Info (332104): Reading SDC File: 'core/core_constraints.sdc' Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Info (332050): set_clock_groups -asynchronous \ -group { bridge_spiclk } \ -group { clk_74a } \ -group { clk_74b } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332174): Ignored filter at core_constraints.sdc(16): core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] could not be matched with a port File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(16): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0]] -phase 0 -name vid_0 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332174): Ignored filter at core_constraints.sdc(17): core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] could not be matched with a port File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(17): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15]] -phase 90 -name vid_90 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332104): Reading SDC File: 'core/core_constraints.sdc' Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Info (332050): set_clock_groups -asynchronous \ -group { bridge_spiclk } \ -group { clk_74a } \ -group { clk_74b } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not match any element of the following types: ( clk ) File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 7 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(16): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0]] -phase 0 -name vid_0 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 16 Warning (332049): Ignored create_generated_clock at core_constraints.sdc(17): Argument -source is an empty collection File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Info (332050): create_generated_clock -divide_by 60 -duty_cycle 50 -master_clock clk74a -source [get_ports core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15]] -phase 90 -name vid_90 File: /home/mcc/work/f/analogue-core-template-amaranth/src/fpga/core/core_constraints.sdc Line: 17 Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFLO is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFHI0 is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Info (332146): Worst-case setup slack is 5.671 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.671 0.000 clk_74a Info (332119): 10.287 0.000 bridge_spiclk Info (332146): Worst-case hold slack is 0.412 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.412 0.000 clk_74a Info (332119): 0.575 0.000 bridge_spiclk Info (332146): Worst-case recovery slack is 9.418 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.418 0.000 clk_74a Info (332146): Worst-case removal slack is 0.735 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.735 0.000 clk_74a Info (332146): Worst-case minimum pulse width slack is 5.395 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.395 0.000 clk_74a Info (332119): 5.850 0.000 bridge_spiclk Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 21.112 ns Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFLO is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFHI0 is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 5.839 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.839 0.000 clk_74a Info (332119): 10.546 0.000 bridge_spiclk Info (332146): Worst-case hold slack is 0.396 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.396 0.000 clk_74a Info (332119): 0.570 0.000 bridge_spiclk Info (332146): Worst-case recovery slack is 9.549 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.549 0.000 clk_74a Info (332146): Worst-case removal slack is 0.926 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.926 0.000 clk_74a Info (332146): Worst-case minimum pulse width slack is 5.293 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.293 0.000 clk_74a Info (332119): 5.827 0.000 bridge_spiclk Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 21.171 ns Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFLO is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFHI0 is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 9.593 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.593 0.000 clk_74a Info (332119): 12.005 0.000 bridge_spiclk Info (332146): Worst-case hold slack is 0.177 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.177 0.000 clk_74a Info (332119): 0.215 0.000 bridge_spiclk Info (332146): Worst-case recovery slack is 11.311 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 11.311 0.000 clk_74a Info (332146): Worst-case removal slack is 0.599 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.599 0.000 clk_74a Info (332146): Worst-case minimum pulse width slack is 5.210 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.210 0.000 clk_74a Info (332119): 6.373 0.000 bridge_spiclk Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 23.860 ns Info: Analyzing Fast 1100mV 0C Model Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFLO is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[0] Warning (332060): Node: core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|ddio_outa[0]~DFFHI0 is being clocked by core_top:ic|amaranth_core:ac|amaranth_core.video_clk_div:video_clk_div|clk_reg[15] Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 9.994 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.994 0.000 clk_74a Info (332119): 12.171 0.000 bridge_spiclk Info (332146): Worst-case hold slack is 0.099 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.099 0.000 clk_74a Info (332119): 0.205 0.000 bridge_spiclk Info (332146): Worst-case recovery slack is 11.546 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 11.546 0.000 clk_74a Info (332146): Worst-case removal slack is 0.540 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.540 0.000 clk_74a Info (332146): Worst-case minimum pulse width slack is 5.162 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 5.162 0.000 clk_74a Info (332119): 6.381 0.000 bridge_spiclk Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 24.123 ns Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 32 warnings Info: Peak virtual memory: 1241 megabytes Info: Processing ended: Tue Nov 7 17:48:27 2023 Info: Elapsed time: 00:00:08 Info: Total CPU time (on all processors): 00:00:13 Info (18207): Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 66 warnings Info (23030): Evaluation of Tcl script /home/mcc/usr/intelFPGA_lite/22.1std/quartus/common/tcl/internal/qsh_flow.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 66 warnings Info: Peak virtual memory: 508 megabytes Info: Processing ended: Tue Nov 7 17:48:28 2023 Info: Elapsed time: 00:00:55 Info: Total CPU time (on all processors): 00:02:38